1. Field of the Invention
The present invention relates to a contents addressable memory (CAM) circuit, and more particularly, to a contents addressable memory circuit, in which a data having an arbitrary bit width can be retrieved at a high speed using a plurality of existing contents addressable memories.
2. Description of the Related Art
The contents addressable memory (CAM) is a memory which inputs a data having a certain bit width and outputs an address in which the data having the same content as the input data is stored. For example, in a data communication apparatus, when a reception data is stored in the contents addressable memory as a storage data, the reception data is stored in an address corresponding to the reception time. Accordingly, when a data having a particular content is inputted later, it is possible to retrieve the reception time of the reception data which is coincident with the particular content.
In such a contents addressable memory, if the storage data having the same bit pattern as the input data exists in a plurality of addresses, a plurality of addresses lines are turned on as coincident address lines. Thus, the contents addressable memory requires an address encoder for specifying one of the coincident address lines in accordance with a certain priority, when a retrieval start address and a data are specified. The address encoder encodes the address line corresponding to the smallest one of addresses subsequent to the retrieval start address or the largest address before the retrieval start address. However, the contents addressable memory having a large memory capacity requires a complicated logic circuit and also requires a processing time. Therefore, various address encoders are proposed. For example, a priority encoder is described in Japanese Laid Open Patent Application (JP-A-Heisei 5-189979) in which a plurality of addresses where a storage data coincident with an input data are stored are outputted one by one.
However, in such a conventional contents addressable memory, the bit width of a data stored in an address is determined on the design of the contents addressable memory. For example, when the bit width of the storage data or of the retrieved data is desired to be expanded, it is necessary to newly design a contents addressable memory having the necessary bit width as a word length. In this case, especially, when the bit width of the manipulated data is long, there is a problem of a cost.